1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a capacitor and a method of manufacturing the same.
2. Description of the Background Art
Structure and manufacturing method of a conventional semiconductor device having a capacitor will be described first.
FIG. 39 is a schematic cross sectional view showing the structure of the conventional semiconductor device. Referring to FIG. 39, an n.sup.+ diffused region 419 is formed on a surface of a p type silicon substrate 417. On this n.sup.+ diffused region 419, an epitaxial 421 is formed. A p.sup.+ diffused region 423 for element isolation is formed to surround a side surface of this epitaxial layer 421.
On a surface of these epitaxial layer 421 and p.sup.+ diffused region 423, an element isolating oxide film 415a and a silicon oxide film 415b are formed.
A p.sup.+ diffused region 401b which is to be a lower electrode of a capacitor is formed on the surface of epitaxial layer 421. An opening 415c is provided in silicon oxide film 415b, reaching a portion of a surface of this p.sup.+ diffused region 401. A silicon nitride film 403 which is to be a capacitor insulating layer is formed, so as to be in contact with p.sup.+ diffused region 401 through this opening 415c. A polycrystalline silicon film 405 to which an impurity is introduced (hereinafter referred to as doped polycrystalline silicon film) is formed to be opposite to p.sup.+ diffused region 401, with this silicon nitride film 403 therebetween. This doped polycrystalline silicon film 405 will be an upper electrode of the capacitor.
Electric charges are stored at the portion where p.sup.+ diffused region 401 and doped polycrystalline silicon film 405 are opposite to one another, forming the capacitor.
An interlayer insulating film 413 consisting of a silicon oxide film or the like is formed entirely over the surface, covering doped polycrystalline silicon film 405 which is to be the upper electrode. In this interlayer insulating film 413, a contact hole 413a exposing a portion of a surface of doped polycrystalline silicon film 405 and a contact hole 413b exposing a portion of a surface of p.sup.+ diffused region 401 are formed. Aluminum layers 411 are formed respectively to be in contact with doped polycrystalline silicon film 405 or p.sup.+ diffused region 401 through each of these contact holes 413a and 413b.
Manufacture of the conventional semiconductor device shown in FIG. 39 together with a bipolar transistor will now be described.
FIGS. 40 to 45 are schematic cross sectional views showing a method of manufacturing the conventional semiconductor device, in order of the steps performed. Referring first to FIG. 40, antimony (Sb) or the like is implanted to a predetermined surface of p type silicon substrate 417. Thereafter, heat treatment is effected thereby forming an n.sup.+ diffused region 419. An epitaxial layer 421 is formed entirely on a surface of p type silicon substrate 417. In this way, a structure is obtained in which n.sup.+ diffused region 419 is buried between p type silicon substrate 417 and epitaxial layer 421.
Then, an element isolating oxide film 415a is formed at a predetermined region of a surface of epitaxial layer 421 by LOCOS (Local Oxidation of Silicon). At the same time, a thin silicon oxide film 415b is also formed.
Thereafter, a p type impurity is implanted to a predetermined region which is isolated by element isolating oxide film 415a and heat treatment is performed. In this way, p.sup.+ diffused region 423 for element isolation is formed at a predetermined region of epitaxial layer 421.
Thereafter, boron is implanted to a predetermined region of epitaxial layer 421. Then, heat treatment is effected thereby forming p.sup.+ diffused regions 401 and 425 at the surface of epitaxial layer 421, which p.sup.+ diffused region 401 formed as lower electrode of the capacitor and p.sup.+ diffused region 425 as a base region of the bipolar transistor.
Referring to FIG. 41, an opening 415c is formed in silicon oxide film 415b by photolithograhpy, exposing a portion of a surface of p.sup.+ diffused region 401. The opposing area of the capacitor is determined by the area of this opening 415c. Silicon nitride film 403 is deposited entirely on the surface so as to be in contact with p.sup.+ diffused region 401 via this opening 415c. Doped polycrystalline silicon film 405 is formed entirely on the surface of this silicon nitride film 403. These silicon nitride film 403 and doped polycrystalline silicon film 405 are patterned by photolithography. In this way, capacitor insulating layer 403 and upper electrode 405 of the capacitor are formed, respectively.
Referring to FIG. 42, interlayer insulating film 413 consisting of silicon oxide film or the like is formed entirely on the surface to cover upper electrode 405. Planarization is effected to this interlayer insulating film 413 so that its upper surface will be planar.
Referring to FIG. 43, a resist pattern 450a having a desired shape is formed on the surface of planarized interlayer insulating film 413. Using this resist pattern 450a as a mask, interlayer insulating film 413 and a silicon oxide film 415b are etched away. Thus, contact hole 413a exposing a portion of a surface of upper electrode 405, contact hole 413b exposing a portion of a surface of p.sup.+ diffused region 401 which is to be the lower electrode, a contact hole 413c exposing a portion of a surface of expitaxial layer 421, together with contact holes 413d and 413e exposing portions of a surface of p.sup.+ diffused region 425 are formed, respectively. Resist pattern 450a is then removed.
Referring to FIG. 44, a resist pattern 450b is formed so as to fill contact holes 413a, 413b and 413d. Under this condition, ions of As (arsenic) are implanted through contact holes 413c and 413e. Resist pattern 450b is then removed.
Referring to FIG. 45, heat treatment is performed, resulting in diffusion and activation of ions implanted through contact holes 413c and 413e. This forms an n.sup.+ diffused region 427 which is to be a collector at the surface of epitaxial layer 421 and an n.sup.+ diffused region 429 which is to be an emitter at the surface of p.sup.+ base diffused region 425. Thereafter, aluminum layer 411 is formed entirely on the surface by sputtering. This aluminum layer 411 is patterned by photolithography to form interconnection layer 411 which is in contact with the underlying layers via contact holes 413a, 413b, 413c, 413d, and 413e, respectively.
To increase degree of integration of the device, it is necessary to reduce the area of the surface that is occupied by each device. However, when the two-dimensional occupation area of the capacitor is reduced, the opposing area of the capacitor electrodes is made smaller, resulting in the reduction of capacitor capacitance. If this capacitance is reduced below a certain value, the IC (Integrated Circuit) is likely to operate inaccurately.
As a means to increase the capacitance of the capacitor with the same two-dimensional occupation area, the capacitor insulating layer between the capacitor electrodes may be made thinner. However, if the capacitor insulating layer is made thin, breakdown voltage between the capacitor electrodes will be decreased.
In general, various voltages such as 5V and 12V are used for an internal voltage of an IC. Considering that search voltage may be applied to the device used for an IC, a breakdown voltage which is at least two times as high as this internal voltage of the IC is needed.
If breakdown voltage between the capacitor electrodes becomes lower than two times the IC internal voltage, there will be a leak current between the electrodes, causing an inaccurate operation of the IC.
In the structure of the capacitor of the conventional semiconductor device, the capacitance and the breakdown voltage was not sufficient when further increase in the integration level was taken into consideration, meaning that when the device is integrated to a higher degree, the operation could be inaccurate.